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xx-xxxx; Rev 0; 2/06
Standard Definition Video Reconstruction Filters and Buffers
General Description
The MAX7428/MAX7430/MAX7432A filters are low-cost, high-performance replacements for standard discrete filter and buffer solutions. The MAX7428/MAX7430/ MAX7432A are ideal for anti-aliasing and DAC smoothing video applications, when analog video is reconstructed from a digital data stream. These devices require a single +5V supply and the filters have a cutoff frequency optimized for NTSC, PAL, and standard definition digital TV (SDTV) video signals. The MAX7428/MAX7430/ MAX7432A feature Maxim's single-pin bus (MSPBTM) interface to digitally control channel selection (IN_A or IN_B), adjust high-frequency boost, bypass the filter, configure luma vs. chroma operation, and control the output disable. The MAX7428 single-channel filter is ideal for composite (CVBS) video signals. The MAX7430 dual filter is optimized for S-Video (Y/C) applications. The MAX7432A triple filter is optimized for component (YPbPr or embedded synchronous RGB) video signals. The MAX7428 is available in a tiny 8-pin SOT23 package, the MAX7430 is available in a miniature 10-pin MAX(R) package, and the MAX7432A is available in a 14-pin TSSOP package. The MAX7428/MAX7430/MAX7432A are fully specified over the -40C to +85C extended temperature range. 6th-Order Lowpass Filter Drives Two 150 Video Loads Four Levels of Passband High-Frequency Boost Control Input 2 to 1 Multiplexer Output Disable Filter Bypassing +5V Single-Supply Voltage Tiny 8-Pin SOT23 Package (MAX7428), 10-Pin MAX Package (MAX7430), and 14-Pin TSSOP Package (MAX7432A)
Features
Ideal for CVBS, Y/C (S-Video), and RGB (Y Pb Pr) Outputs for NTSC, PAL, and SDTV
MAX7428/MAX7430/MAX7432A
Ordering Information
PART MAX7428EKA-T MAX7430EUB MAX7432AEUD TEMP RANGE -40C to +85C -40C to +85C -40C to +85C PINPACKAGE 8 SOT23-8 10 MAX 14 TSSOP TOP MARK AAIU -- --
Applications
Set-Top Boxes DVD Players Hard-Disk Recorders Camcorders
MSPB is a trademark of Maxim Integrated Products, Inc. MAX is a registered trademark of Maxim Integrated Products, Inc. Pin Configurations appear at end of data sheet.
Functional Diagrams
VCC SYNCIO SERIAL INTERFACE AND CONTROL DATA
SYNC
MAX7428
CIN D/A INA 6TH-ORDER FILTER +6dB
75 OUT
*
75 ENCODER CIN INB AUX INPUT GND * *OPTIONAL LEVEL SHIFT BIAS GENERATOR REXT
Functional Diagrams continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Standard Definition Video Reconstruction Filters and Buffers MAX7428/MAX7430/MAX7432A
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................................+6V All Other Pins to GND .................................-0.3V to (VCC + 0.3V) Maximum Current Into Any Pin .........................................50mA Continuous Power Dissipation (TA = +70C) 8-Pin SOT23 (derate 9.71mW/C above +70C)..........777mW 10-Pin MAX (derate 6.94mW/C above +70C) ......555.5mW 14-Pin TSSOP (derate 9.1mW/C above +70C) .........727mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +5V 10%, RREXT = 300k 1%, CIN = 0.1F, CREXT = (1nF to 1F) 1%, CLOAD = 0 to 20pF; BOOST0_, BOOST1_ = 0, 0; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER Passband Response Stopband Attenuation HF Boost Relative Step Size, 4 Levels Differential Gain Differential Phase Harmonic Distortion Signal-to-Noise Ratio Group Delay Deviation Line-Time Distortion Field-Time Distortion Clamp Settling Time Output DC Clamp Level Low-Frequency Gain Group Delay Matching Low-Frequency Gain Matching Channel-to-Channel Crosstalk Output Short-Circuit Current Input Leakage Current Input Dynamic Swing VCC Supply Range AV tg(MATCH) AV(MATCH) XTALK ISC IIN YINp-p CINp-p VCC CLEVEL = 0 CLEVEL = 1 4.5 1.4 0.9 5.5 dG d THD SNR tg Hdist Vdist tclamp Asb SYMBOL CONDITIONS f = 100kHz to 4.2MHz relative to 100kHz f = 100kHz to 5MHz relative to 100kHz f > 27MHz f = 4.2MHz to 5MHz 5-step modulated staircase 5-step modulated staircase f = 100kHz to 5MHz Peak signal (2Vp-p) to RMS noise, f = 100Hz to 50MHz Deviation from 100kHz to 3.58 (4.43)MHz 18s, 100 IRE bar 130 lines, 18s, 100 IRE bar to 1% (Note 1) CLEVEL = 0 CLEVEL = 1 Gain at 100kHz Low frequency channel-to-channel matching f = 100kHz Channel-to-channel gain matching, f = 100kHz Channel-to-channel crosstalk, f = 100kHz to 5.5MHz OUT_ shorted to ground or VCC -60 50 10 0.8 1.35 1.9 1.975 2 5 72 20 0.3 0.5 100 1.3 1.85 2.05 MIN -0.5 -1.0 48 0.2 0.4 0.2 0.2 0.1 0.5 0.6 TYP MAX +0.5 +1.0 UNITS dB dB dB % degrees % dB ns % % Lines V V/V ns % dB mA A Vp-p V
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Standard Definition Video Reconstruction Filters and Buffers
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +5V 10%, RREXT = 300k 1%, CIN = 0.1F, CREXT = (1nF to 1F) 1%, CLOAD = 0 to 20pF; BOOST0_, BOOST1_ = 0, 0; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER Supply Current Power-Supply Rejection Ratio IN_A/IN_B Crosstalk LOGIC CHARACTERISTICS Logic Input High Voltage Logic Input Low Voltage Logic Input Current Logic Output High Voltage Logic Output Low Voltage VIH VIL IIH/IIL VOH VOL VIL = 0 (source), VIH = VCC (sink) I(SOURCE) = 500A I(SINK) = 500A VCC 0.5 0.4 2 0.8 10 V V A V V SYMBOL ICC PSRR No load CONDITIONS MAX7428 MAX7430 MAX7432A VIN = 100mVp-p, f = 0 to 5.5MHz VIN = 100mVp-p, f = 100kHz to 5.5MHz MIN TYP 24 45 68 40 -60 MAX 32 62 86 dB dB mA UNITS
MAX7428/MAX7430/MAX7432A
MSPB INTERFACE TIMING SPECIFICATIONS
(VCC = +5V 10%, RREXT = 300k 1%, CREXT = (1nF to 1F) 1%, CLOAD = 0 to 20pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Figures 4 through 9)
PARAMETER MSPB TIMING Logic-Zero/Prompt Pulse Width Logic-One Pulse Width Transaction Pulse Width Separation Between Pulses Bus Release Time by Host After Prompt Pulse Bus Reclaim Time by Host After Prompt Pulse Read Back Data Valid Window After the Prompt Pulse t0, tP t1 tT tWAIT tRELEASE tRECLAIM tREAD 13 2.3 4.7 1 24 80 0.5 1 5 30 100 8 36 120 s s s s s s s SYMBOL CONDITIONS MIN TYP MAX UNITS
Note 1: One horizontal line = 63.5s. Note 2: MAX7428 devices are 100% production tested at TA = +25C and are guaranteed by design from TA = TMIN to TMAX.
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Standard Definition Video Reconstruction Filters and Buffers MAX7428/MAX7430/MAX7432A
Typical Operating Characteristics
(VCC = +5V, RREXT = 300k; BOOST0_, BOOST1_ = 0, 0; VIN_ = 1Vp-p, TA = +25C, unless otherwise noted.)
AMPLITUDE vs. FREQUENCY
MAX7428/30/32 toc01
PASSBAND AMPLITUDE vs. FREQUENCY
MAX7428/30/32 toc02
PHASE RESPONSE vs. FREQUENCY
MAX7428/30/32 toc03
0 -10 AMPLITUDE (dB) -20 -30 -40 -50 -60 0.1 1 10
2 A 0 AMPLITUDE (dB) -2 -4 -6 -8 -10 C
B
180 120 PHASE (DEGREES) 60 0 -60 -120 -180
D
A: BOOST1, BOOST0 = 1, 1 B: BOOST1, BOOST0 = 1, 0 C: BOOST1, BOOST0 = 0, 1 D: BOOST1, BOOST0 = 0, 0 0.1 1 FREQUENCY (MHz) 10
100
0.1
1 FREQUENCY (MHz)
10
FREQUENCY (MHz)
GROUP DELAY vs. FREQUENCY
MAX7428/30/32 toc04
2T RESPONSE (1IRE = 7.14mV)
MAX7428/30/32 toc05
MODULATED 12.5T RESPONSE (1IRE = 7.14mV)
MAX7428/30/32 toc06
120 100 GROUP DELAY (ns) 80 60 40 20 0 0.1 1 FREQUENCY (MHz)
INA_ 200mV/div
INA_ 200mV/div
OUT_ 200mV/div
OUT_ 200mV/div
10
200ns/div
400ns/div
SUPPLY CURRENT vs. TEMPERATURE
MAX7428/30/32 toc07
DIFFERENTIAL GAIN
MAX7428/30/32 toc08
DIFFERENTIAL PHASE
-0.06 0 DIFFERENTIAL PHASE (DEGREES) 0.20 0.15 0.10 0.05 0 0.04 0.06 0.06 0.04 0.02
MAX7428/30/32 toc09
28 27 SUPPLY CURRENT (mA) 26 25 24 23 NO LOAD 22 -40 -15 10 35 60
0.2
0
-0.01
-0.04
-0.08
-0.10
DIFFERENTIAL GAIN (%)
0.1
0 -0.1 -0.2 -0.3
-0.05 1st. 2nd. 3rd. 4th. 5th. 6th. 1st. 2nd. 3rd. 4th. 5th. 6th.
85
TEMPERATURE (C)
4
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Standard Definition Video Reconstruction Filters and Buffers MAX7428/MAX7430/MAX7432A
Typical Operating Characteristics (continued)
(VCC = +5V, RREXT = 300k; BOOST0_, BOOST1_ = 0, 0; VIN = 1Vp-p, TA = +25C, unless otherwise noted.)
OUTPUT TRANSIENT DUE TO INPUT MUX SWITCHING
MAX7428/30/32 toc11 MAX7428/30/32 toc10
OUTPUT IMPEDANCE vs. FREQUENCY
4.0 3.5 3.0 IMPEDANCE () 2.5 2.0 1.5 1.0 0.5 OUT_ 500mV/div
PASSBAND CHANNEL-TO-CHANNEL CROSSTALK vs. FREQUENCY
MAX7428/30/32 toc12
-70
-75 CROSSTALK (dB)
-80
-85
-90 BOOST = CODE 00
0 0.1 1 FREQUENCY (MHz) 10 200ns/div
-95 0.1 1 FREQUENCY (MHz) 10
Pin Description
PIN MAX7432A 1 2 3 4, 10 5 6 7 8 9 11 12 MAX7430 1 2 -- 8 4 5 -- 6 -- 7 3 MAX7428 -- -- -- 4 -- -- -- 6 -- -- 7 NAME IN1A IN2A IN3A GND IN1B IN2B IN3B DATA OUT3 OUT2 REXT FUNCTION Video Input 1A. Master channel, sync signal required. Use a 0.1F series input capacitor for proper operation. Video Input 2A. Slave channel, clamping controlled by master channel sync. Use a 0.1F series input capacitor for proper operation. Video Input 3A. Slave channel, clamping controlled by master channel sync. Use a 0.1F series input capacitor for proper operation. Ground Video Input 1B. Master channel, sync signal required. Use a 0.1F series input capacitor for proper operation. Video Input 2B. Slave channel, clamping controlled by master channel sync. Use a 0.1F series input capacitor for proper operation. Video Input 3B. Slave channel, clamping controlled by master channel sync. Use a 0.1F series input capacitor for proper operation. Serial Data Interface Buffer Output 3 Buffer Output 2 External Resistor. Connect a 300k resistor from REXT to GND for internal biasing. Connect a 1nF to 1F capacitor from REXT to GND for chip-address programming (see Table 3).
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Standard Definition Video Reconstruction Filters and Buffers MAX7428/MAX7430/MAX7432A
Pin Description (continued)
PIN MAX7432A 13 14 -- -- -- -- MAX7430 9 10 -- -- -- -- MAX7428 -- 2 1 3 5 8 NAME OUT1 VCC INA INB SYNCIO OUT Buffer Output 1 +5V Supply Voltage Video Input A. Use a 0.1F series input capacitor for proper operation. Video Input B. Use a 0.1F series input capacitor for proper operation. Sync Pulse Input or Output Buffer Output
75 **220F Z0 = 75 5V 0.1F D/A *1M INA VCC OUT C1 Z0 = 75 75 75 **220F
FUNCTION
75
MAX7428
REXT INB DATA ***
300k
0.1F D/A *1M ENCODER GND
SERIAL I/O 5V 10k SYNC PULSE IN OR OUT C1 = 1nF TO 1F (SEE TABLE 3) *NEEDED ONLY IN FILTER BYPASS MODE **OPTIONAL CAPACITOR ***ONLY ONE PULLUP RESISTOR NEEDED PER BUS
SYNCIO
Figure 1. MAX7428 Typical Application Circuit
Detailed Description
The MAX7428/MAX7430/MAX7432A filter and buffer the outputs of DAC encoder chipsets that process digital video information in applications such as set-top boxes, hard-disk recorders, DVD players, recorders, and digital VCRs. These devices also filter and "clean-up" analog video signals. Each channel in the MAX7428/ MAX7430/MAX7432A includes an input mux to select the input channel, a 6th-order Sallen-Key filter with four adjustable high-frequency boost levels, an output buffer with a 6dB gain, a sync detector and clamp, and an external resistor to set internal bias levels. Output disable adds additional multiplexing in a wired-OR configuration. Filter bypass, in conjunction with the two inputs, can be used to provide filtered and unfiltered video signal processing. Maxim's Single Pin Bus
(MSPB) interface controls all of the above features. An external capacitor is used to assign each device a unique address that allows control of up to 16 devices on the same bus. Typical application circuits for the MAX7428/MAX7430/MAX7432A are shown in Figures 1, 2, and 3.
Input Considerations
Use a 0.1F ceramic capacitor to AC-couple the input to the MAX7428/MAX7430/MAX7432A. This input capacitor stores a DC level to level-shift the input signal to an optimal point between VCC and GND. The ABSEL bit on the Control Register sets which channel (IN_A or IN_B) is selected (Control Register section). The IN_A and IN_B inputs have a typical input resistance of 50k.
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Standard Definition Video Reconstruction Filters and Buffers MAX7428/MAX7430/MAX7432A
75 200F** Z0 = 75
+5V
75 VCC 0.1F AUX IN *1M DATA 0.1F D/A ENCODER *1M 75 IN1B 75 IN1A OUT1 *** +5V 10k SERIAL I/O 200F** Z0 = 75 75 75 200F** Z0 = 75
MAX7430
0.1F AUX IN *1M 300k 0.1F D/A ENCODER *1M GND C1 = 1nF TO 1F (SEE TABLE 3) *NEEDED ONLY IN FILTER BYPASS MODE **OPTIONAL OUTPUT CAPACITOR ***ONLY ONE PULLUP RESISTOR NEEDED PER BUS IN2B REXT C1 IN2A OUT2 75 75 200F** Z0 = 75
Figure 2. MAX7430 Typical Application Circuit
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Standard Definition Video Reconstruction Filters and Buffers MAX7428/MAX7430/MAX7432A
75 +5V
220F**
Z0 = 75
75
VCC 0.1F AUX IN *1M 0.1F D/A ENCODER *1M 0.1F AUX IN *1M 0.1F D/A ENCODER *1M 0.1F AUX IN *1M OUT3 0.1F D/A ENCODER *1M IN3B GND REXT IN3A IN2B IN2A IN1B IN1A DATA OUT1 ***
75
220F**
Z0 = 75
+5V SERIAL I/O
75
75
220F**
Z0 = 75
75
MAX7432
75 OUT2 75 220F** Z0 = 75
75
220F**
Z0 = 75
75 220F** Z0 = 75
75
75
300k C1 = 1nF TO 1F (SEE TABLE 3) *NEEDED ONLY IN FILTER BYPASS MODE **OPTIONAL OUTPUT CAPACITOR ***ONLY ONE PULLUP RESISTOR NEEDED PER BUS
C1
Figure 3. MAX7432A Typical Application Circuit
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Standard Definition Video Reconstruction Filters and Buffers MAX7428/MAX7430/MAX7432A
Table 1. MAX7428 Control Register
(MSB) NAME DEFAULT SYNCIO 0 ABSEL 1 BYPASS 1 CLEVEL 0 BOOST1 0 BOOST0 0 OUTDISABLE 0 FIRST BIT (LSB) -- 0
Filter
Filter Response The reconstruction filter consists of a 6th-order Butterworth filter in three second-order stages. The Butterworth filter features a maximally flat passband for NTSC and PAL bandwidths. The stopband offers typically 50dB of attenuation at sampling frequencies of 25MHz and above (see Typical Operating Characteristics). The corner frequency is not critical since the response of the filter meets both the stopband and passband specifications. The MAX7428/MAX7430/MAX7432A incorporate an autotrimming feature that reduces the corner frequency variation digitally. It is possible, although not likely, that a discrete shift in the corner frequency may occur due to an external environmental change. The autotrimming operates continuously so that the corner frequency remains centered over the full operating temperature range. High-Frequency Boost The high-frequency boost compensates for signal degradation and roll-off in the signal path prior to the MAX7428/ MAX7430/MAX7432A. High-frequency boost is programmable in four steps to increase image sharpness.
Serial Interface
Maxim's Single Pin Bus (MSPB) interface uses DATA to transfer data to and from the microprocessor (P) and the MAX7428/MAX7430/MAX7432A. This negative logic protocol uses three different pulse widths to represent a logic "1", logic "0", and control commands. MSPB allows up to 16 devices to be connected on the same bus by assigning a unique 4-bit identification address to each device. The P can communicate to each device individually or by sending a "broadcast" message to all the devices. The unique address for each device is set by means of the time constant set by the external capacitor connected in parallel with the external 300k resistor (see Initializing the MAX7428/ MAX7430/MAX7432A section).
MAX7428 Control Register
Table 1 defines the structure of the MAX7428 8-bit control register programmed by MSPB. This register controls the selection of INA or INB, SYNCIO functionality, filter bypassing, clamp-level selection, high-frequency boost control, and output disable. See Maxim's Single Pin Bus Interface (MSPB) section for detailed programming instructions. SYNCIO: SYNCIO Select bit. A logic 0 sets the SYNCIO pin to function as an output while a logic 1 sets SYNCIO to function as an input. ABSEL: Channel Select bit. A logic 0 selects the input at INB to be processed while a logic 1 selects the input at INA to be processed. BYPASS: Filter Bypass Select bit. A logic 1 selects the filter while a logic 0 bypasses the filter.
Output Buffer
The output buffer is able to drive two 150 video loads with a 2Vp-p signal. The +6dB gain of the output buffer is independent of the filter bypass or input selection. The output buffer drives the 75 backmatch resistors and series capacitor (typically 220F). The MAX7428/ MAX7430/MAX7432A are able to drive the video load directly without using the 220F capacitor. This feature is common in SCART applications. The OUTDISABLE bit of the control register disables the output (mute) (see Control Register section).
Table 2. Boost Level Programming
BOOST1 0 0 1 1 BOOST0 0 1 0 1 RELATIVE HIGH FREQUENCY BOOST 0 0.3db to 0.5db 0.6db to 1.0db 0.9db to 1.5db
Filter Bypass
The MAX7428/MAX7430/MAX7432A offer selectable filter bypassing that allows either of the video inputs to be filtered or unfiltered. The 1M optional input resistors are needed only in filter bypass mode to provide a discharge path for the input coupling capacitors.
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Standard Definition Video Reconstruction Filters and Buffers MAX7428/MAX7430/MAX7432A
Table 3. MAX7430 Control Register
(MSB) NAME DEFAULT -- 0 ABSEL2 1 BYPASS2 1 CLEVEL2 0 BOOST1(2) 0 BOOST0(2) 0 OUT DISABLE2 0 -- 0
NAME DEFAULT
-- 0
ABSEL1 1
BYPASS1 1
CLEVEL1 0
BOOST1(1) 0
BOOST0(1) 0
OUT DISABLE1 0
-- 0 FIRST BIT (LSB)
CLEVEL: Clamp Level bit. A logic 0 selects a clamp level of 1V while a logic 0 selects a clamp level of 1.5V at the output. [BOOST1, BOOST0]: High-Frequency Boost Control bits. The adjust bits select the amount of high-frequency boost for the filter. Table 2 defines four levels of adjustment. OUTDISABLE: Output Disable bit. A logic 0 selects normal operation while a logic 1 places the output in a high-impedance state.
Table 4. Boost Level Programming
BOOST1_ 0 0 1 1 BOOST0_ 0 1 0 1 RELATIVE HIGH FREQUENCY BOOST 0 0.3dB to 0.5dB 0.6dB to 1.0dB 0.9dB to 1.5dB
MAX7430 Control Register
Table 3 defines the structure of the MAX7430 16-bit control register programmed by MSPB. This register controls the selection of IN_A or IN_B, selection of filter 1 or 2, filter bypassing, clamp-level selection, high-frequency boost control, and output disable. See Maxim's Single Pin Bus Interface (MSPB) section for detailed programming instructions. ABSEL_: Channel Select bit. A logic zero selects the input at IN_B to be processed while a logic 1 selects the input at IN_A to be processed. BYPASS_: Filter Bypass Select bit. A logic 1 selects the channel filter while a logic 0 bypasses the channel filter. CLEVEL_: Clamp Level bit. A logic 0 selects a channel clamp level of 1V while a logic 0 selects a channel clamp level of 1.5V at the output. [BOOST1_, BOOST0_]: High-Frequency Boost Control bits. The adjust bits select the amount of high-frequency boost for the channel filter. Table 4 defines four levels of adjustment. OUTDISABLE_: Output Disable bit. A logic 0 selects normal channel output operation while a logic 1 puts the channel output in a high-impedance state.
MAX7432A Control Register
Table 5 defines the structure of the MAX7432A 24-bit control register programmed by MSPB. This register controls the selection of IN_A or IN_B, selection of filter 1, 2, or 3, filter bypassing, clamp-level selection, highfrequency boost control, and output disable. See Maxim's Single-Pin Bus Interface (MSPB) section for detailed programming instructions. ABSEL_: Channel Select bit. A logic zero selects the input at IN_B to be processed while a logic 1 selects the input at IN_A to be processed. BYPASS_: Filter Bypass Select bit. A logic 1 selects the channel filter while a logic 0 bypasses the channel filter. CLEVEL_: Clamp Level bit. A logic 0 selects a channel clamp level of 1V while a logic 0 selects a channel clamp level of 1.5V at the output. [BOOST1_, BOOST0_]: High-Frequency Boost Control bits. The adjust bits select the amount of high-frequency boost for the channel filter. Table 6 defines four levels of adjustment. OUTDISABLE_: Output Disable Bit. A logic 0 selects normal channel output operation while a logic 1 puts the channel output in high-impedance state.
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Standard Definition Video Reconstruction Filters and Buffers MAX7428/MAX7430/MAX7432A
Table 5. MAX7432A Control Register
(MSB) NAME DEFAULT -- 0 ABSEL3 1 BYPASS3 1 CLEVEL3 0 BOOST1(3) 0 BOOST0(3) 0 OUT DISABLE3 0 OUT DISABLE2 0 OUT DISABLE1 0 -- 0
NAME DEFAULT
-- 0
ABSEL2 1
BYPASS2 1
CLEVEL2 0
BOOST1(2) 0
BOOST0(2) 0
-- 0
NAME DEFAULT
-- 0
ABSEL1 1
BYPASS1 1
CLEVEL1 0
BOOST1(1) 0
BOOST0(1) 0
-- 0 FIRST BIT (LSB)
Applications Information
Maxim's Single Pin Bus (MSPB) Serial Interface
The MSPB interface uses three pulses of different widths to represent commands and data bits. Figure 4 shows the set of pulses that the single pin interface uses to communicate with the device. A combination of the one pulse (t1), zero pulse (t0), transaction pulse (tT), and prompt pulse (tP), writes to, reads back from, and sends broadcast data to the devices on the bus. Note: The zero pulse and prompt pulse are the same. Initialization pulses are significantly longer and are used only on power-up or software reset.
Table 6. Boost Level Programming
BOOST1_ 0 0 1 1 BOOST0_ 0 1 0 1 RELATIVE HIGH FREQUENCY BOOST 0 0.3dB to 0.5dB 0.6dB to 1.0dB 0.9dB to 1.5dB
Initializing the MAX7428/MAX7430/MAX7432A
Initialization is performed only after power-up or software reset. It assigns a unique address to each device on the bus. The time constant of the capacitor connected to REXT in parallel with the 300k resistor determines the order in which the devices are initialized (address assigned). The device with the largest time constant is initialized first and so on, in descending order. Table 7 shows the "Initialize Wait" and "Initialize Time" pulse widths needed for a specific capacitor value and tolerance. Program each device on the bus with this command sequence starting with the device with the biggest capacitor. To reinitialize a device, cycle the power or use a software reset. The following is the command sequence and timing diagram (Figure 5) for initialization as shown below. Chip ID is entered LSB first. Note: If there is only one device on the bus, no initialization is needed. Communicate to the device using the broadcast command described on page 13.
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ZERO/PROMPT PULSE
t0
tP = t0 = 5s
ONE PULSE
t1
t1 = 30s
TRANSACTION PULSE
tT
tT = 100s
Figure 4. MSPB Interface Pulses
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Standard Definition Video Reconstruction Filters and Buffers MAX7428/MAX7430/MAX7432A
Table 7. Initialization Capacitor Values and Pulse Widths (CREXT = 10% Tolerance, RREXT = 1% Tolerance)
CAPACITOR VALUE (nF) 1000 680 470 220 150 100 68 47 22 15 10 6.8 4.7 2.2 1.5 1 INITIALIZING WAIT PERIOD (ms) (tINTWAIT) 20.000 13.600 9.400 4.400 3.000 2.000 1.360 0.940 0.440 0.300 0.200 0.136 0.094 0.044 0.030 0.020 INITIALIZING TIME PERIOD (ms) WITH RREXT = 300k (tINT) MIN 162 (136.8) 112 52.6 (44.1) 35.90 23.90 (13.7) 16.25 11.21 (4.4) 5.26 3.59 2.39 1.625 (1.37) 1.121 0.526 (0.441) 0.359 0.239 0.162 (0.137) TYP 171 (144) 118 55.4 (46.4) 37.80 25.20 (14.4) 17.10 11.80 (4.64) 5.54 3.78 2.52 1.710 (1.44) 1.180 0.554 (0.464) 0.378 0.252 0.171 (0.144) MAX 179 (151.2) 123 58.2 (48.72) 39.70 26.50 (15.1) 17.95 12.39 (4.9) 5.82 3.97 2.65 1.795 (1.51) 1.239 0.582 (0.487) 0.397 0.265 0.179 (0.151)
Note: ( ) Indicates the time periods associated with 20% capacitors. This limits the maximum number of devices on the bus to seven.
Initialization Command Sequence: Initialize wait T011 Initialize Time Address ID = 4-bits T111
than 8/16/24 bits are loaded into the register. The following is the command sequence and timing diagram (Figure 7) for a write sequence.
Write Command Sequence: Data 8-bits (MAX7428, See Table 1) Data 16-bits (MAX7430, See Table 3) Data 24-bits (MAX7432A, See Table 5)
Programming the MAX7428/MAX7430/MAX7432A
An address sequence precedes a write or read operation to determine with which device to communicate. If the address transmitted in this mode matches with a device's address, the device and P can initiate data transfer. When entering the four address bits, ensure that the LSB is entered first. The following is the command sequence and timing diagram (Figure 6) for an address sequence.
Address Command Sequence: T010 Address = 4-bits T111
T001
T111
Use a write sequence to load data into the data register of the device. It must follow an address sequence. Transmit a minimum of eight data bits for the MAX7428, 16 data bits for the MAX7430, or 24 data bits for the MAX7432A to make this transaction valid starting with the LSB first. The last 8/16/24 data bits are used if more
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During the read sequence, the P sends a prompt pulse causing the device to output the data word LSB first. Similar to the write transaction, the read transaction must be preceded by an address sequence. If more than 8 prompts (MAX7428), 16 prompts (MAX7430), or 24 prompts (MAX7432A) are available, the device outputs the same data starting with the LSB again. The following is the command sequence and timing diagram (Figure 8) for a read sequence.
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Standard Definition Video Reconstruction Filters and Buffers MAX7428/MAX7430/MAX7432A
Read Command Sequence: T101 Prompts 8 (MAX7428) Prompts 16 (MAX7430) Prompts 24 (MAX7432A) T111 Software Reset Command Sequence: T000 8 or more 1s (MAX7428) 16 or more 1s (MAX7430) 24 or more 1s (MAX7432A) OR T010 T001 Address = 4-bits 8 or more 1s (MAX7428) 16 or more 1s (MAX7430) 24 or more 1s (MAX7432A) T111 T111 T111
The broadcast sequence writes data to the control registers of all the devices on the bus at the same time. Write data with the LSB first. The following is the command sequence and timing diagram (Figure 9) for the broadcast transaction. No address sequence is required. Use the broadcast command when there is only one device on the bus.
Broadcast Command Sequence: T000 Data 8-bits (MAX7428) Data 16-bits (MAX7430) Data 24-bits (MAX7432A) T111
more ones for the MAX7430, or 24 or more ones for the MAX7432A to that device register.
Composite Video Filtering
The MAX7428 is ideally suited for filtering composite video signals. Program the SYNCIO as an output when processing composite video signals. In the rare occasion that an external sync pulse is needed to process the composite video, program the SYNCIO as an input.
Executing a software reset serves the same function as a power-on reset and is achieved by transmitting all data bits (eight or more) for the MAX7428, sixteen or
tWAIT tINTWAIT tT t0 t1 t1 tINT t1
ADDRESS: 0001 t0 t0 t0 tT t1 t1 t1
LSB
MSB
Figure 5. Initialization Timing Diagram
tWAIT tT t0 t1 t0 t1
ADDRESS: 0001 t0 t0 t0 tT t1 t1 t1
LSB
MSB
Figure 6. Address Timing Diagram
tWAIT
DATA: 1***000 t0 t0 t1 t0 t0 t0 t1 tT t1 t1 t1
tT
LSB
MSB
Figure 7. Write Timing Diagram ______________________________________________________________________________________ 13
Standard Definition Video Reconstruction Filters and Buffers MAX7428/MAX7430/MAX7432A
tWAIT tO A B CD t0 A B CD
tT
t1
t0
t1
tP
HIGH-Z
0 OR 1
tP
0 OR 1 0 OR 1
tP
tT
t1
t1
t1
READS 1ST BIT (LSB) A: P WILL RELEASE BUS BY TIME A
READS 2ND BIT
REPEAT TO READ 6 MORE BITS
C: P HAS UNTIL TIME C TO FINISH READING BIT D: DEVICE WILL RELEASE BUS BY TIME D
B: P CAN START READING BIT AT TIME B
NOTE: TIME A, B, C, D ARE REFERENCED TO t0.
Figure 8. Read Timing Diagram
tWAIT
DATA: 1***000 t0 t0 t0 t0 t0 t0 t1 tT t1 t1 t1
tT
LSB
MSB
Figure 9. Broadcast Timing Diagram
When processing composite video set the clamp level to +1V (CLEVEL = 0). Use the MAX7430 to process two synchronous composite signals simultaneously. Use the MAX7432A to process three synchronous composite signals simultaneously.
Y/C Video Filtering
The MAX7430 is ideally suited for processing S-Video (Y/C) signals (Figure 10). Ensure that IN1_ filters the signal that contains the sync information (Y) since the clamping on IN2_ is internally controlled by the master channel (IN1_) sync. Set the clamp level for IN1_ to +1V (CLEVEL1 = 0) and set the clamp level for IN2_ to +1.5V (CLEVEL2 = 1). Use two MAX7428s for Y/C video filtering. Since only the Y signal contains the sync, a typical Y/C video-filtering application requires a master-slave configuration of the SYNCIO. The MAX7428 processing the Y signal should have SYNCIO configured as an output, which in turn drives the SYNCIO of the second MAX7428, processing the C signal that has its SYNCIO configured as an input (Figure 11). Clamping level for the Y signal should be set for +1V (CLEVEL = 0), and clamping level for the C signal should be set for +1.5V (CLEVEL = 1). Use the MAX7432A to filter one Y/C and one composite video signal that are synchronous.
Component video consists of three separate signals. Typically the three signals are separate red, green, and blue (RGB) signals or Y (luma) and two color difference signals: B-Y (Pb) which is blue minus luma and R-Y (Pr), which is red minus luma. Sync information is included with the Y signal of Y Pb Pr component video, or in the case of RGB, sync is usually carried on the G or on a separate H sync line. The MAX7432A is ideally suited for filtering component video signals. Ensure that the sync signal (Y for Y Pb Pr signals and usually G for RGB signals) is filtered by IN1_ since IN2_ and IN3_ are internally synced to IN1_. Set the clamp level for IN1_ to +1V (CLEVEL1 = 0) and set the clamp levels for IN2_ and IN3_ to +1.5V (CLEVEL2, 3 = 1) for Y Pb Pr filtering (Figure 12) and set all clamp levels to 1V (CLEVEL_ = 0) for RGB filtering (Figure 13). A Y Pb Pr component video-filter application requires three MAX7428s with SYNCIO master-slave configuration. The MAX7428 processing the Y signal has its SYNCIO configured as an output, which in turn drives the SYNCIO inputs of the other MAX7428s (Figure 14). For RGB video signal filtering with a separate horizontal sync signal, configure all MAX7428s for SYNCIO as an input (Figure 15).
Component Video (RGB or Y Pb Pr) Filtering
14
______________________________________________________________________________________
Standard Definition Video Reconstruction Filters and Buffers MAX7428/MAX7430/MAX7432A
Y (LUMA) INA OUT SYNCIO
MAX7430
Y (LUMA) IN1A [CLEVEL = 0] OUT1
(CLEVEL = 0)
MAX7428
C (CHROMA) C (CHROMA) IN2A [CLEVEL = 1] OUT2
INA
OUT SYNCIO (CLEVEL = 1)
MAX7428
Figure 10. MAX7430 Y/C Video Filter Application
Figure 11. Y/C Video Filter Application
MAX7432
Y (LUMA) (INCLUDES SYNC SIGNAL) IN1A [CLEVEL = 0] OUT1 G (MUST CONTAIN SYNC SIGNAL) IN1A
MAX7432
[CLEVEL = 0] OUT1
Pb
IN2A
[CLEVEL = 1]
OUT2
R
IN2A
[CLEVEL = 0]
OUT2
Pr
IN3A
[CLEVEL = 1]
OUT2
B
IN3A
[CLEVEL = 0]
OUT3
Figure 12. MAX7432A Y Pb Pr Video Filter Application
Figure 13. MAX7432A RGB Video Filter with Embedded Sync Application
Set the clamping levels for component video so the MAX7428 processing Y clamps at +1V (CLEVEL = 0). The remaining two MAX7428s should have clamp levels set to +1.5V (CLEVEL = 1). For RGB video with external sync (H), all three MAX7428s should have clamp levels set to +1V (CLEVEL = 0).
Power-Supply Bypassing and Layout
The MAX7428/MAX7430/MAX7432A operate from a single +5V supply. Bypass VCC to GND with a 0.1F capacitor. Place all external components as close to the devices as possible. Refer to the MAX7428EVKIT for a proven PC board layout example.
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15
Standard Definition Video Reconstruction Filters and Buffers MAX7428/MAX7430/MAX7432A
Y (LUMA) (INCLUDES SYNC SIGNAL) INA INB OUT SYNCIO (CLEVEL = 0)
R INA INB OUT SYNCIO (CLEVEL = 0)
MAX7428
MAX7428
G
INA INB
OUT SYNCIO (CLEVEL = 0)
Pb
INA INB
OUT SYNCIO (CLEVEL = 1)
MAX7428
MAX7428
B INA INB OUT SYNCIO (CLEVEL = 0)
Pr
INA INB
OUT SYNCIO (CLEVEL = 1)
MAX7428
EXTERNAL H SYNC
MAX7428
Figure 14. Y Pb Pr Video Filter Application
Figure 15. RGB Video Filter with External Sync Application
Chip Information
TRANSISTOR COUNT: MAX7428 = 4955 MAX7430 = 7413 MAX7432A = 9873 PROCESS: BiCMOS
16
______________________________________________________________________________________
Standard Definition Video Reconstruction Filters and Buffers
Pin Configurations
TOP VIEW
MAX7428/MAX7430/MAX7432A
INA VCC INB
1 2
8 7
OUT REXT DATA SYNCIO
IN1A 1 IN2A REXT IN1B 2 3 4 5
10 VCC 9 OUT1 GND OUT2 DATA
IN1A 1 IN2A IN3A 2 3
14 VCC 13 OUT1 12 REXT
MAX7428
3 6 5
MAX7430
8 7 6
GND 4 IN1B 5 IN2B 6 IN3B 7
MAX7432
11 OUT2 10 GND 9 8 OUT3 DATA
GND 4
IN2B
SOT23
MAX
TSSOP
Functional Diagrams (continued)
VCC *
IN1A D/A 6TH-ORDER FILTER IN1B LEVEL SHIFT AUX INPUT SYNC +6dB OUT1 *
SERIAL INTERFACE AND CONTROL
DATA *
D/A ENCODER
IN2A 6TH-ORDER FILTER IN2B LEVEL SHIFT AUX INPUT MAX7430 GND BIAS GENERATOR REXT +6dB OUT2
*
*OPTIONAL OUTPUT CAPACITOR
______________________________________________________________________________________
17
Standard Definition Video Reconstruction Filters and Buffers MAX7428/MAX7430/MAX7432A
Functional Diagrams (continued)
VCC
*
IN1A D/A 6TH-ORDER FILTER IN1B LEVEL SHIFT AUX INPUT SYNC SERIAL INTERFACE AND CONTROL DATA +6dB OUT1
*
*
D/A
IN2A 6TH-ORDER FILTER IN2B LEVEL SHIFT AUX INPUT +6dB OUT2
*
*
D/A
IN3A 6TH-ORDER FILTER +6dB OUT3
*
ENCODER
IN3B LEVEL SHIFT AUX INPUT MAX7432 GND BIAS GENERATOR REXT
*OPTIONAL OUTPUT CAPACITOR
18
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Standard Definition Video Reconstruction Filters and Buffers
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
SOT23, 8L.EPS
MAX7428/MAX7430/MAX7432A
MARKING
0
0
PACKAGE OUTLINE, SOT-23, 8L BODY
21-0078
H
1 1
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19
Standard Definition Video Reconstruction Filters and Buffers MAX7428/MAX7430/MAX7432A
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
10LUMAX.EPS
20
______________________________________________________________________________________
Standard Definition Video Reconstruction Filters and Buffers MAX7428/MAX7430/MAX7432A
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
TSSOP4.40mm.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21 (c) 2006 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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